The present invention relates to content addressable memory (CAM). In particular, the present invention relates to a circuit and method for reducing power consumption of search lines and match lines in a CAM device.
In many conventional memory systems, such as random access memory, binary digits (bits) are stored in memory cells, and are accessed by a processor that specifies a linear address that is associated with the given cell. This system provides rapid access to any portion of the memory system within certain limitations. To facilitate processor control, each operation that accesses memory must declare, as a part of the instruction, the address of the memory cell/cells required. Standard memory systems are not well designed for a content based search. Content based searches in standard memory require software based algorithmic search under the control of the microprocessor. Many memory operations are required to perform a search. These searches are neither quick nor efficient in using processor resources.
To overcome these inadequacies an associative memory system called Content Addressable Memory (CAM) has been developed. CAM allows cells to be referenced by their contents, so it has first found use in lookup table implementations such as cache memory subsystems and is now rapidly finding use in networking systems. CAM""s most valuable feature is its ability to perform a search and compare of multiple locations as a single operation, in which search data is compared with data stored within the CAM. Typically search data is loaded onto search lines and compared with stored words in the CAM. During a search-and-compare operation, a match or mismatch signal associated with each stored word is generated on a matchline, indicating whether the search word matches a stored word or not. A typical CAM block diagram is shown in FIG. 1. The CAM 10 includes a matrix, or array 100, of CAM cells (not shown) arranged in rows and columns. For a ternary CAM, the cells are typically either DRAM or SRAM type, and store one of three states: logic xe2x80x9c1xe2x80x9d, logic xe2x80x9c0xe2x80x9d and xe2x80x9cdon""t carexe2x80x9d, as two bits of data. A predetermined number of CAM cells in a row store a word of data. An address decoder 12 is used to select any row within the CAM array 100 to allow data to be written, via write data register 17, into or read out of the selected row. Although most commonly, data is written or loaded into the CAM and searched. Data access circuitry such as bitlines and column selection devices, are located within the array 100 to transfer data into and out of the array 100. The comparand, mask registers 15, search data register 500 and write data registers 17 receive data from the data I/O block 20. Located within CAM array 100 for each row of CAM cells are matchline sense circuits (not shown). The matchline sense circuits are used during search-and-compare operations for outputting a result indicating a successful or unsuccessful match of a search word against the stored word in the row. The results for all rows are processed by the priority encoder 400 to output the address (Match Address) corresponding to the location of a matched word. The match address is stored in match address registers 300 before being output by the match address output block 26. Since it is possible that more than one row will match the search word, the priority encoder 400 generates the highest priority address corresponding to a matched word. Search data register 500 is responsible for asserting search word data onto the searchlines within the array 100. Each search data register 500 receives its respective data signals (not shown), for driving one bit of the search word data onto a pair of complementary searchlines. Additional components of the CAM include the control circuit block 14, the flag logic block 16, the voltage supply generation block 18, various control and address registers 22 and a refresh counter 28.
CAM cells are generally either SRAM based cells or DRAM based cells. Until recently, SRAM based CAM cells have been most common because of their speed and compatibility with standard logic processes. However, to provide ternary CAMs, i.e. CAMs having cells which store one of three possible states: a xe2x80x9c0xe2x80x9d, xe2x80x9c1xe2x80x9d or xe2x80x9cdon""t carexe2x80x9d, ternary SRAM based cells typically require many more transistors compared to a typical DRAM based cell of six transistors. As a result, ternary SRAM based CAMs have a much lower packing density than ternary DRAM cells. FIG. 2 shows a typical ternary DRAM type CAM cell 101 as described in Canadian Patent Application No. 2,266,062, filed Mar. 31, 1999, the contents of which are incorporated herein by reference. Cell 101 has a comparison circuit which includes an n-channel search transistor 102 connected in series with an n-channel compare transistor 104 between a matchline ML and a tail line TL. A search line SL is connected to the gate of search transistor 102. The storage circuit includes an n-channel access transistor 106 having a gate connected to a wordline WL and connected in series with capacitor 108 between bitline BL and a cell plate voltage potential VCP. Charge storage node CELL1 is connected to the gate of compare transistor 104 to turn on transistor 104 if there is charge stored on capacitor 108 i.e. if CELL1 is logic xe2x80x9c1xe2x80x9d. The remaining transistors and capacitor replicate transistors 102, 104, 106 and capacitor 108 for the other half of the ternary data bit, and are connected to corresponding lines SL* and BL* and are provided to support ternary data storage. Together they can store a ternary value representing logic xe2x80x9c1xe2x80x9d, logic xe2x80x9c0xe2x80x9d, or xe2x80x9cdon""t carexe2x80x9d.
Lines SL, SL*, BL and BL* are common to all cells of the column, and lines ML, TL and WL are common to all cells of a word in the row. The tail line TL is typically connected to ground and all the transistors are n-channel transistors. The description of the operation of the ternary DRAM cell is detailed in the aforementioned reference.
FIG. 3 shows a typical SRAM cell of the prior art used to implement the ternary CAM cell. The SRAM type CAM cell of FIG. 3 includes a CMOS cross-coupled latch connected to a pair of bitlines via access transistors. The cross-coupled latch consists of p-channel transistors 110 and 111, and n-channel transistors 112 and 113, where p-channel transistor 110 and n-channel transistor 112, and p-channel transistor 111 and n-channel transistor 113, form respective complimentary pairs connected in series between the VDD voltage supply and ground. N-channel access transistor 114 couples bitline BL to the shared source-drain of transistors 110 and 112, and n-channel access transistor 115 couples bitline BL* to the shared source-drain of transistors 111 and 113. The gates of access transistors 114 and 115 are connected to a common wordline WL for the row. A single output line 116 connects the shared source-drain of transistors 111 and 113 to the comparison circuit of FIG. 4. Since the CAM cell of FIG. 3 only stores one bit of information, a second identical circuit would be required to store a second bit of information in order to provide ternary data storage. It will be apparent to one skilled in the art that a ternary SRAM type CAM cell is implemented with many more transistors than the previously discussed ternary DRAM type CAM cell shown in FIG. 2.
FIG. 4 shows a ternary comparison circuit of the prior art used with the ternary SRAM type CAM cell previously discussed in FIG. 3. The circuit compares stored CAM cell data against searchline data, and discharges a precharged matchline to indicate the mis-match condition. Otherwise, the precharged matchline remains at the precharge voltage to indicate the match condition. The ternary comparison circuit of FIG. 4 consists of n-channel compare transistors 120 and 122 connected in series between searchlines SL and SL*, and n-channel diode connected transistor 118 coupling the matchline ML to the shared source-drain of n-channel compare transistors 120 and 122. Although the combination of the ternary SRAM type CAM cell with the ternary comparison circuit is more commonly used in conventional CAM arrays, substitution with the ternary DRAM type CAM cell of FIG. 2 will significantly reduce the area of the array.
To search the ternary DRAM CAM cell of FIG. 2 for example, the searchlines SLj and SLj* are required to carry three logic level combinations: xe2x80x9cLOW,HIGHxe2x80x9d and xe2x80x9cHIGH,LOWxe2x80x9d to represent the xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9ddata states respectively, and xe2x80x9cLOW,LOWxe2x80x9d to represent the xe2x80x9cdon""t carexe2x80x9d or mask state. With the exception of the mask state, during any search-and-compare operation, at least one searchline of a pair of searchlines will be at the high logic level of VDD and the other searchline will be at the low logic level of ground. For a match condition to occur between search and stored data, there must be no conduction path between ML and TL, whereas for a mis-match condition, conduction will occur between ML and TL. If a xe2x80x9cdon""t carexe2x80x9d is stored in a cell, that cell will be unable to form a connection between ML and TL, regardless of the data presented on the searchlines, and thus will not affect the outcome of the word compare operation. The discharge path between ML and TL is formed when at least one pair of search and compare transistors, such as transistors 102 and 104 for example, are turned on. Power consumption is a critical issue in CAM""s because, unlike RAMs, each cell in a CAM is active on every search cycle, using significant power for charging and discharging both matchlines and searchlines. In conventional CAMs for example, all searchlines are held at the low logic level of ground during the precharge phase. In the active phase, the appropriate searchlines are driven to the high logic level of VDD. When the comparison between the stored words and the search word is completed, the precharge phase is entered and all searchlines are grounded in preparation for the next search-and-compare operation. This scheme suffers from high power consumption because searchlines are cycled between VDD and ground for every search-and-compare operation. Since it is possible that successive search words do not change substantially, ie. only single bit changes, considerable power is unnecessarily consumed when the same searchlines are grounded and then driven back to VDD for the next search-and-compare operation.
New techniques for saving matchline power is disclosed in commonly owned application U.S. Pat. No. 2,307,240 filed May 1, 2000, the contents of which are incorporated herein by reference. However, overall power consumption of conventional CAM is still high due to the requirement for cycling the searchlines as previously discussed.
An improved searchline control circuit developed for the matchline sense circuit in U.S. Pat. No. 2,307,240 is shown in FIG. 8, and discussed in more detail later. This searchline control circuit latches the search data, keeping the pair of searchlines at either one of the xe2x80x9cLOW,HIGHxe2x80x9d, xe2x80x9cHIGH,LOWxe2x80x9d and xe2x80x9cLOW,LOWxe2x80x9d states during a search-and-compare operation. In a subsequent search-and-compare operation, new search data is latched, and the pair of searchlines either remains in the same state or is driven to a different state. In this scheme, only searchlines with new data change states, thereby reducing the power consumption as compared to previous searchline control schemes. However, when search data changes from one data state to the other data state (xe2x80x9c0xe2x80x9dto xe2x80x9c1xe2x80x9d, or xe2x80x9c1xe2x80x9dto xe2x80x9c0xe2x80x9d) the voltage levels on the corresponding pair of searchlines must change to their opposite polarities. If the searchline capacitance is charged or discharged in one cycle, then the worst case power dissipation in each searchline is given by the equation:
P=CSLxc3x97V2xc3x97(f/2)
Where CSL is the capacitance of the search line, V is the supply voltage and f is the search frequency. Hence, power consumption is still relatively high due to the rail-to-rail voltage changes in the searchlines. Additionally, larger CAM arrays employing longer searchlines will add more parasitic capacitance which must be overcome by the searchline control circuits.
It is therefore desirable to provide a searchline control circuit capable of consuming very little power and operating at high speed.
It is an object of the present invention to obviate or mitigate at least one disadvantage of previous searchline control circuits and methods. In particular, it is an object of the present invention to provide a searchline control circuit and method of operation that has reduced power consumption and that operates at high speed.
In a first aspect, the present invention provides a control circuit for reducing power consumption in first and second signal lines in a semiconductor device. The circuit includes a data buffer, first and second coupling circuits, and an equalizing circuit. The data buffer drives data on the first and second signal lines. The first and second coupling circuits disconnect the first and second signal lines, respectively, from the data buffer in response to an enable signal. The equalizing circuit shorts the pair of complementary signal lines together in response to the enable signal.
In one embodiment, the data buffer includes a latch circuit and a drive circuit. The latch circuit receives a data signal, a mask signal and a control signal, and provides, in response to the control signal, a first output corresponding to the data signal, and a second output corresponding to the mask signal. The drive circuit receives the first output and the second output, and generates data on the first and second signal lines. In this embodiment, the drive circuit includes a first logic gate and a second logic gate. The first logic gate receives the first output and the second output from the latch circuit, and generates a first data logic level on the first signal line. The second logic gate receives an inverted first output and the second output, and generates a second data logic level on the second signal line.
In further embodiments of the control circuit of the present invention, the first and second coupling circuits can include tri-state buffers or transmission gates. The equalizing circuit includes a logic circuit, and a transmission gate, and can include a transistor of either n-type or p-type. The logic circuit generates the enable signal. In a further aspect of this embodiment, the logic circuit generates the enable signal when the data and new data are different.
In a further aspect of the present invention, there is provided a control circuit for reducing searchline power consumption in a content addressable memory. The circuit includes a flip-flop, coupling circuit, enabling circuit and an equalizing circuit. The flip-flop receives search data and provides first and second search data outputs. The coupling circuit couples the first and second search data outputs to first and second searchlines. The enabling circuit selectively enables the coupling circuit to pass the first and second data outputs to the first and second searchlines in response to a precharge signal. The equalizing circuit connects the first and second searchlines together in response to the precharge signal.
In further embodiments of the control circuit of the present invention, the flip-flop can be a D-type flip-flop which receives mask data and a clock signal. The D-type flip-flop latches the search data and the mask data and provides the first and second search data outputs in response to a rising edge of the clock signal. In a further aspect of this embodiment, the coupling circuit includes a first logic gate, a second logic gate and first and second buffers. The first logic gate receives the first and second search data outputs for generating the first intermediate search data output. The second logic gate receives an inverted first search data output and the second search data output for generating a second intermediate data output. The first and second buffers selectively couple the first and second intermediate data outputs to the first and second searchlines respectively. In a further aspect of this embodiment, the first and second buffers can be tri-state buffers or transmission gates, and the equalizing circuit can be either an n-type transistor or a p-type transistor. In yet another futher aspect of this embodiment, the enabling circuit includes a logic circuit for receiving the search data and the first search data output to enable the equalizing circuit when the search data and the first search data output are different, in response to the precharge signal.
In a further aspect of the present invention, there is provided a content addressable memory. The content addressable memory consists of an array of content addressable memory cells arranged in rows and columns, an address decoder, write data circuitry, search data circuitry, matchline sense circuitry, and a searchline control circuit. The address decoder addresses rows of cells. The write data circuitry writes data to the cells. The search data circuitry writes search data onto pairs of searchlines. The matchline sense circuitry compares data stored in the cells to the search data on the pairs of searchlines. The searchline control circuit selectively equalizes the pairs of searchlines during a precharge phase. In a further aspect of this embodiment, the matchlines and tail lines of the matchline sense circuitry are equalized during the precharge phase.
In a presently preferred embodiment, the present invention provides a control circuit for reducing searchline power consumption in a content addressable memory. This control circuit preferably consists of a flip flop for latching a search data signal and a mask data signal in response to a clock signal, and for providing first and second search data outputs. A first inverter receives first search data output to provide an inverted search data output. A first logic gate receives the inverted search data output and the second search data output, to provide a first intermediate search data output, while a second logic gate receives the first search data output and the second search data output, to provide a second intermediate search data output. A third logic gate receives the clock signal, and a precharge signal, to provide an equalization signal. A second inverter receives equalization signal to provide an enable signal. A first buffer circuit selectively couples the first intermediate search data output to a first searchline in response to the enable signal while a second buffer circuit selectively couples the second intermediate search data output to a second searchline in response to the enable signal. A transistor has a source connected to the first searchline, a drain connected to the second searchline and a gate connected to the equalization signal. Preferably, the first and second logic gates are NOR gates, and the first and second coupling circuits are either tri-state buffers, or transmission gates. The transistor can be an n-type or p-type transistor.
In a further aspect, the present invention provides a method for precharging first and second complementary signal lines in a content addressable memory. The method consists of latching search data during a precharge cycle; driving the first and second complementary signal lines with the latched search data during an active cycle; and equalizing the first and second complementary signal lines before latching new search data in a subsequent precharge cycle. The first and second signal lines can be driven to complementary data logic levels, or to the same logic levels. Generally, the first and second signal lines are equalized to a mid-point voltage level between a high logic voltage level, such as VDD, and a low logic voltage level, such as ground. In a further aspect of this embodiment, equalization of the first and second complementary signal lines is disabled when the search data and the new search data are at the same logic levels.
In yet another preferred embodiment, the present invention provides a control circuit for reducing searchline power consumption in a content addressable memory. This control circuit preferably consists of a flip flop for latching a search data signal and a mask data signal in response to a clock signal, and for providing first and second search data outputs. A first inverter receives first search data output to provide an inverted search data output. A first logic gate receives the inverted search data output and the second search data output, to provide a first intermediate search data output, while a second logic gate receives the first search data output and the second search data output, to provide a second intermediate search data output. A third logic gate receives the clock signal, and a precharge signal, to provide an intermediate control signal. A second inverter receives the intermediate control signal to provide an enable signal. A first buffer circuit selectively couples the first intermediate search data output to a first searchline in response to the enable signal while a second buffer circuit selectively couples the second intermediate search data output to a second searchline in response to the enable signal. A fourth logic gate receives the search data and the first search data output to provide a second intermediate control signal. A fifth logic gate receives the second intermediate control signal and the enable signal to provide an equalization signal. A transistor has a source connected to the first searchline, a drain connected to the second searchline and a gate connected to the equalization signal.
In a further aspect of the present invention, there is provided a control circuit for reducing searchline power consumption in a content addressable memory. The circuit includes a flip-flop, coupling circuit, enabling circuit, an equalizing circuit and a logic circuit. The flip-flop receives search data and provides first and second search data outputs. The coupling circuit couples the first and second search data outputs to first and second searchlines. The enabling circuit selectively enables the coupling circuit to pass the first and second data outputs to the first and second searchlines in response to a precharge signal. The equalizing circuit is connected between the first and second searchlines. The logic circuit receives the search data and the first search data output to enable the equalizing circuit, in response to the precharge signal, when the search data is different from the search data output.